IBM has unveiled a new chip design that crams 100 billion transistors onto a surface the size of a fingernail – a breakthrough the company says is the world’s first known sub-1 nanometre technology. The current industry standard hovers around 2nm, but IBM’s prototype is the equivalent of 0.7nm, achieved by stacking transistor sheets on top of each other like a towering skyscraper.
Transistors are the tiny switches that power everything from smartphones to data centres, and the more that can be squeezed onto a chip, the more powerful it becomes. IBM claims its NanoStack architecture delivers 50% better performance than its own 2nm chip while using 70% less energy. Jay Gambetta, director of IBM Research, called it a “landmark moment” for the future of chips. “We’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” he said.
“IBM unveils first sub-1nm chip with 100 billion transistors, claiming 50% better performance and 70% energy efficiency.”
The approach marks a shift away from traditional planar design. For decades, transistor density doubled every two years – a trend known as Moore’s Law – but that pace is becoming harder to sustain. Chipmakers have turned to 3D alternatives, essentially building transistors taller. IBM now takes that further by layering sheets of them. Professor Alan Woodward, a computer scientist at Surrey University, compared the technique to urban planning. “IBM’s NanoStack is like proposing a 100-storey skyscraper,” he said.
Despite the breakthrough, it will be several years before the technology reaches production. IBM debuted similar performance leaps with its 2nm chip in 2021, but that chip has yet to hit the market at scale. The company’s new design, however, could extend Moore’s Law further and fuel the energy-intensive demands of generative AI and streaming. For now, the prototype remains a proof of concept – one that, like a skyscraper, will take time to build.