IBM has unveiled a new chip design it says could enable manufacturers to cram 100 billion transistors onto a silicon chip the size of a fingernail — a breakthrough the company describes as a “landmark moment” for the future of computing.
The chip technology, which IBM claims is the equivalent of around 0.7 nanometres (nm), may be the world’s first known chip technology below 1nm. The current industry standard is around 2nm. In tests, the prototype performed 50% better than IBM’s own 2nm chip and was 70% more energy efficient, the firm said.
“IBM claims world's first sub-1nm chip tech, packing 100 billion transistors per fingernail-sized chip”
But the technology will take several years to reach production. IBM debuted its 2nm chip tech in 2021, which at the time also produced similar leaps in performance and energy efficiency.
Jay Gambetta, director of IBM Research and IBM Fellow, said: “With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Transistors are the building blocks of silicon chips, which power smartphones, games consoles, laptops and the powerful computers in data centres that handle streaming, online banking and the generative AI boom. The more transistors that can be squeezed onto a chip, the more powerful it becomes, and designers strive to make chips ever smaller.
For decades, the number of transistors on a chip has doubled every two years — a phenomenon known as Moore’s Law. But with billions already on some chips, sustaining that pace is increasingly difficult. To extend it, chip designers have focused on 3D alternatives, altering transistor shapes to make them taller. IBM’s approach layers sheets of them on top of each other.
Professor Alan Woodward, a computer scientist at Surrey University, compared the NanoStack design to building a big block of flats rather than houses in a city. “IBM’s NanoStack is like proposing a 100-storey skyscraper,” he said.