IBM has unveiled a new chip design it says could enable manufacturers to cram 100 billion transistors onto a surface the size of a fingernail, by building transistors upwards like a skyscraper instead of laying them out flat.
The breakthrough, which the company calls NanoStack, is the equivalent of around 0.7 nanometres — a billionth of a metre, the size of a few atoms — and is believed to be the world’s first known chip technology below 1nm. The current industry standard is around 2nm.
“IBM claims world's first sub-1nm chip tech, using 'NanoStack' architecture to stack transistors like a skyscraper.”
In tests, IBM claims its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient — similar leaps to those it reported when it debuted its 2nm technology in 2021.
But it will be several years before the chip tech is ready to go into production, the company said.
Jay Gambetta, director of IBM Research and IBM Fellow, described NanoStack as a “landmark moment” for the future of chips. “With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” he said.
Transistors are the building blocks of silicon chips that power smartphones, games consoles, laptops and the data centres behind streaming, online banking and generative AI. The more transistors manufacturers can squeeze onto a chip, the more powerful it becomes. For decades the number of transistors on a chip has doubled every two years, a phenomenon known as Moore’s Law, but experts broadly agree this pace cannot continue indefinitely.
To extend the law, chip designers have focused on 3D alternatives, making transistors taller. IBM’s approach is to layer sheets of them on top of each other. Professor Alan Woodward, a computer scientist at Surrey University, compared it with building a big block of flats rather than houses in a city. “IBM’s NanoStack is like proposing a 100-storey skyscraper,” he said.